8 Bit Processor in CISC architecture, Built on Breadboard

TTL Transistor Logic Chips used

Running Assembly Language

Adjustable Processor Clock Speed from 10 Hz to 10,000 Hz with TLC555 Chip

Manual Mode Operation Option (for Debugging Purpose)

Includes: Clock Module, Address Counter, Eprom Address Registers, Eprom and I/OUnits, Eprom Instruction Registers, Assembly Code EPPROM and counters, Micro Code EPPROMs (4 Registers), 32 Instruction Process Capacity, BUS Input Output Pins, Debugging Units (Data Reading Interface and Eprom Edit Buttons), A and B register (Memory Blocks) (2 x 8 Bit Data) for mathematical operation